1. Field of the Invention
The present invention relates to methods and apparatus for performing floating point mathematical operations in an information processing system and, more particularly, to methods and apparatus for controlling the operation of a floating point unit in executing floating point instructions.
2. Description of the Prior Art
In many information processing systems it is necessary, or at least desirable, to be able to perform floating point mathematical operations, for example, in performing the mathematical calculations involved in the technical and scientific fields. While some few computers are designed specifically for scientific and technical applications, the majority of systems are designed for general purpose applications and the problem becomes one of providing the specialized capability for floating point operations in a geneal purpose system.
The approaches used in the past to provide this capability may be generally referred to as emulation, an independent floating point processor and an associated floating point processor. In the first, floating point operations are performed by means of floating point emulation software running on the system's general purpose central processing unit. That is, software which makes the central processor operate like, or emulate, a floating point processor. Because a general purpose central processing unit is generally not designed for floating point operations, the central processing unit is generally both slow and inefficient in performing these operations. This approach has therefore been unsatisfactory except where the frequency of floating point operations is low enough that the inefficiencies and lack of speed are acceptable.
In the other extreme, some systems are provided with a completely separate and independent floating point processor which operates in parallel with the central processor for the specific purpose of performing floating point operations. While an independent floating point processor is may be quite fast and efficient at floating point operations, it generally represents a substantial investment in terms of system cost. That is an independent floating point, processor will, in general, have all of the operating elements and thus cost, of a general purpose central processing unit but is usable only for the special function of performing floating point operations. In addition, the central processing unit, the floating point unit and the system as a whole will be more complex, and thus more expensive, due to the inherent complexities of a system having more than one independent processing unit. This approach has therefore been fully justified only in systems primarily dedicated to scientific and technical applications.
In the third and most common approach, the central processor unit is provided with an associated floating point unit which essentially operates as an addition or extension to the arithmetic and logic unit in the central processing unit. That is, the associated floating point unit will contain the specialized arithmetic and logic elements for floating point operations and will share other elements, such as the instruction and operand fetch and decode mechanisms and microcode control mechanisms, of the central processing unit.
The principal problem with this approach is in obtaining a desirable speed of operation of both the central processing unit and the floating point unit. That is, due to the sharing of elements either the central processing unit or the floating point unit must delay operation until the other unit has completed its operations. For example, in many systems the central processing unit will perform memory read and write operations and certain control functions for the floating point unit, so that the central processing unit must suspend execution of its own operations to service the floating point unit during floating point operations. Likewise, the floating point unit must frequently delay the execution of operations until the central processing unit is free to provide support for the floating point unit.
The present invention provides improved methods and apparatus for executing floating point operations which solves these and other problems of the prior art.